1. Field of the Invention
The present invention generally relates to a method for manufacturing a device having a conductive via, and more particularly to a method for manufacturing a device having a conductive via wherein the predetermined aspect ratio of a through hole of a dielectric material layer can be substantially increased.
2. Description of the Related Art
Components located on the active surface of a semiconductor device become smaller in size as the geometric shape of the semiconductor device becomes gradually smaller. For example, the passive component (e.g. a capacitor) is constituted by two metallic layers and one conductive via. In order to decrease the volume of the capacitor, it is necessary to decrease the area of the metallic layers. Also, it is necessary to have a high aspect ratio for the conductive via. A conventional method for manufacturing a device having a conductive via generally utilizes the photosensitive benzocyclobutene (BCB) to act as a low-k dielectric material layer. However, the size of the conductive via is limited by the property of a polymer material of the negative-type photosensitive BCB when the conductive via having a small size is formed by exposing and developing the photosensitive BCB.
Referring to FIG. 1, it depicts a conventional semiconductor device 10. The semiconductor device 10 includes a silicon substrate 12, a plurality of metallic traces 16 and a low-k dielectric material layer 30 of a photosensitive BCB. The silicon substrate 12 is provided with a plurality of pads 15 adapted to be electrically connected to an integrated circuit (IC) (not shown) located on an active surface. The metallic traces 16 are disposed on the silicon substrate 12 and are electrically connected to the pads 15. The dielectric material layer 30 of the photosensitive BCB is patterned by exposing and developing processes, thereby defining through holes 20. A metallic material 22 is electroplated in the through hole 20 so as to form a conductive via 24 electrically connected to the metallic trace 16. The dielectric material layer 30 of the photosensitive BCB is made of a negative-type polymer material, and thus the resolution is not good when the through hole 20 is formed by exposing and developing the dielectric material layer 30 of the photosensitive BCB. The through hole 20 formed in the dielectric material layer 30 of the photosensitive BCB has an upper opening and a lower opening wherein the hole diameter of the upper opening is wider than that of the lower opening. Thus, the size of the conductive via 24 cannot be very small. Generally, considering the photosensitive BCB having a thickness t1 of 5 μm, the through hole 20 formed has a hole diameter d1 of 30 μm at most. Thus, the aspect ratio (the ratio of depth t1 to width d1) of the conductive via 24 must be limited to less than ⅙. Also, when a small-sized conductive via 24 is formed in the dielectric material layer 30 of the photosensitive BCB by the exposing and developing processes, it is easy to leave some residual BCB in the conductive via 24 and is hard to remove the some residual BCB. Thus, manufacturing and electrical problems tend to rise in the subsequent processes.
Referring to FIGS. 2 to 8, they depict a conventional method for manufacturing a device having a high aspect ratio via. Referring to FIG. 2, a silicon substrate 52 is provided, wherein the silicon substrate 52 has at least one pad 54 adapted to be connected to integrated circuits (ICs) (not shown) on an active surface. A seed metallic layer 56 is formed on the silicon substrate 52 and is electrically connected to the pad 54. A positive-type photosensitive photoresist layer 58 is formed on the silicon substrate 52 and the seed metallic layer 56. Referring to FIG. 3, the photoresist layer 58 is patterned by exposing and developing processes, thereby defining at least one through hole 62 exposing the seed metallic layer 56. The positive-type polymer material has better resolution during the exposing and developing processes, and thus the diameter of the through hole 62 of the photoresist layer 58 is smaller and the through hole 62 further has a high aspect ratio.
Referring to FIG. 4, at least one metallic material is electroplated in the through hole 62, thereby forming a metallic pillar 64, which is electrically connected to the seed metallic layer 56. Referring to FIG. 5, the photoresist layer 58 is removed. Referring to FIG. 6, a low-k dielectric material layer 66 made of negative-type benzocyclobutene (BCB) is coated on the silicon substrate 52, thereby sealing the seed metallic layer 56 and the metallic pillar 64. Referring to FIG. 7, the low-k dielectric material layer 66 is patterned by exposing and developing processes, thereby exposing a top surface of the metallic pillar 64. Referring to FIG. 8, a metallic trace 68 is formed on the low-k dielectric material layer 66 and is electrically connected to the metallic pillar 64.
However, after the coating process the low-k dielectric material layer 66 made of BCB is not located on a flat surface so as to affect the subsequent process for manufacturing the metallic trace 68.
Accordingly, there exists a need for method for manufacturing a device having a conductive via capable of solving the above-mentioned problems.